FPGA tutorials > Blink

Description

This tutorial will give you a brief introduction on how to build new functions into the programmable logic (PL) on your Red Pitaya. You will need a basic understanding of combinatorial and sequential logic - gates and flip-flops - to understand and complete the exercise. I will also assume some familiarity with the hardware description language (HDL) Verilog. Usage instructions for the Vivado tools will be kept to what is necessary in order to complete the tutorial. There are plenty of good tutorials for the tools available from Xilinx and other sources.

The tutorial will cover the following topics:

  • Installing Vivado FPGA programming environment
  • Opening, building and loading the Red Pitaya tutorial project
  • Modifying the tutorial project to make a "hello world" Blink LED

Required hardware

  • Red Pitaya

Installing Vivado FPGA programming environment

1. Download Vivado 2013.3

We recommend to use the full installer with SDK because the SDK will be useful for C-development later on.
Download All OS Vivado and SDK Full Installer, package size is about 6.8GB. (sometimes this can take few hours)
For downloading you must have Xilinx account, if not then create one.

2. Download free WebPACK licence

Download WebPack free licence. This is not necessary step because when you start installing Vivado it will open licence manager where you can chose WebPack option and automatically download free licence. This option, dependent on system which are you using don’t always work.
We recommend downloading WebPack licence manually and when installing process demand licence you will import it from your PC.

- With your account Sign in on Xilinx page
- Go to My account (top of the page)
- Set (don’t click) mouse pointer on Support option on menu bar
- Find Downloads and Licensing
- Click to Get License file
- Web page will open your account data, click next
- Chose Vivado WebPack license and download

*If you have already downloaded licence with existing account this option will be disabled

3. Donwload Lab Tools 14.6

Go to ISE Design Tools and chose Lab Tools 14.6 (end of the page)

4. Download and unpack the red_pitaya_fpga_blink_example project to your home directory.

5. Install Vivado 2013.3

- Go to folder where you have downloaded Xilinx_Vivado_SDK_2013.3_1017_1.tar, extract it
- Open Terminal and go to Xilinx_Vivado_SDK_2013.3_1017_1 folder
- Run xsetup.exe with command

sudo ./xsetup

- Follow installation process
- Select Vivado System Edition + SDK
- Import your license

6. Install Lab Tools 14.6

- Go to folder where you have downloaded Xilinx_LabTools_14.6_P.68d_3.tar, extract it
- Open Terminal and go to Xilinx_LabTools_14.6_P.68d_3 folder
- Run xsetup.exe with command

sudo ./xsetup

Opening, building and loading the Red Pitaya tutorial project

Open the tutorial project

Start Vivado, choose "Open Project" from the "Getting Started" section and browse to the folder with the tutorial project. Select the file "red_pitaya.xpr" and open it.
Click to see screenshot

Overview of the project

The Red Pitaya FPGA code is made of four components, HDL sources, an IP block design, constraints and simulation sources.The three things first mentioned contribute to the resulting logic design, while the fourth is important during the design phase but has no direct influence on the output product. In the "Project Manager" you will find all three parts, the HDL sources and block design in the section "Design Sources" and the constraints in the section "Constraints".

HDL sources are listed with "instance name - module name (sourcefile name) (nr of child-instances)". The design sources are organized into a hierarchical tree view that represents the instance structure of the project. Note that the module "red_pitaya_top" has no instance name, because it is the entry point of the design (root of the tree) and therefore not instantiated from within the design. Constraints describe physical constraints that the design has to meet, like for example the IO port configuration - port direction, IO standard (3.3V CMOS, 1.5V high speed differential, ...). Since they relate to the external design of the system (read: the Red Pitaya hardware), we will have no need to touch them.

Click to see screenshot

The IP block design is also listed in the hierarchy of "Design Sources", but can be accessed from the "IP Integrator" section in the "Flow Navigator" as well. When opened, the schematical diagram of the block design will be displayed. Click to see screenshot. If you have clicked on Open Block Design and get following error java.lang.NumberFormatException: For input string: "0,8" then you probably have native language setting.
You can solve that with changing locale file on your PC
- Open Terminal
- Input sudo nano /etc/default/locale
- Delete all and replace with folowing:

LANG=en_US.utf8
LANGUAGE=nb_NO:nb:no_NO:no:nn_NO:nn:en
LC_CTYPE="en_US.utf8"
LC_NUMERIC="en_US.utf8"
LC_TIME="en_US.utf8"
LC_COLLATE="en_US.utf8"
LC_MONETARY="en_US.utf8"
LC_MESSAGES="en_US.utf8"
LC_PAPER="en_US.utf8"
LC_NAME="en_US.utf8"
LC_ADDRESS="en_US.utf8"
LC_TELEPHONE="en_US.utf8"
LC_MEASUREMENT="en_US.utf8"
LC_IDENTIFICATION="en_US.utf8"
LC_ALL=

Building the FPGA bitstream

Before you start to modify the design, we recommend to build it in its original state to verify that everything is working as expected, and also to get acquainted with the synthesis/implementation process of the FPGA tools.
- Click on Run Synthesis
- Click on Run Implementation
- Click on Generate Bitstream

Each of these steps can be executed separately if the preceding steps completed successfully. If the preceding steps have not yet been completed, Vivado will ask you whether you want the intermediate steps to be executed automatically. Say yes and optionally tell Vivado not to ask you again next time. The build process will take about 3 minutes, depending on your machine. If you change a HDL sourcefile, everything from synthesis forward will be invalidated and will need to be rerun. If you change a block design, this block design and everything from synthesis forward will be invalidated.

When everything built successfully, the project summary page will look like this The generated bitstream "red_pitaya_top.bit" will be in the folder red_pitay/red_pitaya.runs/impl_1. There is one thing to bear in mind when using "Generate Bitstream" to do a full build: It will not re-run the synthesis if there already was a successful synthesis run, even if it is now out-of-date due to changes made to the source files. In that case, either start "Run Synthesis" manually or delete the previous run (right click "Synthesis" and select "Reset Synthesis Run").

Preparing a loadable FPGA image for /dev/xdevcfg

During development, the easiest way to load a new FPGA bitstream into the ZYNQ is via the reconfiguration device /dev/xdevcfg . However, the standard issue Red Pitaya can not load the red_pitaya_top.bit directly, it has to be converted into a prom file via the promgen utility from the Lab Tools. The following console command prepares the Lab Tools environment (assuming a 64bit machine and Lab Tools default installation). Open terminal and input:

source /opt/Xilinx/14.6/LabTools/settings64.sh

Go to your red_pitaya/red_pitaya.runs/impl_1 folder

cd /home/...path to red_pitaya folder.../red_pitaya/red_pitaya.runs/impl_1

Then build the loadable prom file "fpga.bin" with this command:

promgen -w -b -p bin -o fpga.bin -u 0 red_pitaya_top.bit -data_width 32

Open new Terminal and connect to your Red Pitaya with SSH and enable writing to Red Pitaya

ssh root@your Red Pitaya IP
redpitaya> rw

Go back to Terminal where are you in red_pitaya/red_pitaya.runs/impl_1 folder and copy the file "fpga.bin" to your Red Pitaya's /tmp folder

scp fpga.bin root@your Red Pitaya IP:/tmp

Go back to Terminal where are you on Red Pitaya check if you have copy fpga.bin

redpitaya> cd /tmp
redpitaya>ls

Load fpga.bin to xdevcfg with

redpitaya> cat /tmp/fpga.bin >/dev/xdevcfg

The new logic will become active immediately, but will be lost after a reboot. This is ideal for experimenting with a new logic design. If something goes really wrong and you can no longer even use the console to load a new bitstream, all you need to do is reboot the system.

You may have noticed that the yellow LED 0 stopped flashing when you loaded the new bitstream. That is because the tutorial project does not yet have any "flashing logic" connected to the LEDs. You will also find that none of the Bazaar applications works anymore. That is because the registers in the 0x40100000-0x407fffff region are no longer there and will read constant 0. In the next section of this tutorial, we will start to put functionality back into the device.

Modifying the project to make a "hello world" flashing LED

After you have built and run the tutorial project in the previous chapter, and saw that it does basically nothing, let's get right to it and make it do something tangible. As promised in the caption, we will say "hello world" by cheerfully flashing with one of the LEDs 0-7. We will put our new logic into the red_pitaya_hk module because that is the place where the LEDs are handled now. The module declares a couple of external connections, including outputs to the LEDs, a clock and a reset signal. We will need all of those in our new logic.

red_pitaya_hk

red_pitaya_hk already has some simple logic for the LEDs. This is the place where we are going to add ours.Right now there are 8 registers which hold the state of the 8 LEDs and an assignment of the registers' outputs to the outgoing connections led_o. First order of business is to generate a clock for the flashing LED. It should be slow enough for the eye to resolve, let's say about 2Hz. There is one clock 'sys_clk_i' already present in red_pitaya_hk which runs at 125MHz. If we feed that into a 26 bit counter, the highest bit will toggle at a frequency of about 1.9Hz. To make LED 3 flash with 1.9Hz, all we need to do now is to connect led_o[3] to led_counter[25] instead of led_reg[3].

Delete code from line 78 to line 85 and replace with following code:
reg [8-1:0] led_reg;
reg [25:0] led_counter;
always @(posedge sys_clk_i) begin
if (!sys_rstn_i) begin led_counter <= 26'h0; end else begin led_counter <= led_counter + 26'h1; end end assign led_o = {led_reg[7:4],led_counter[25],led_reg[2:0]};

IT SHOULD LOOK LIKE THIS

Save the changes, build (REPEAT steps from "Building the FPGA bitstream" part) the new logic and try it out.